1. Represent gates and combinational logic by concurrent VHDL statements.
2. Make a table and derive the characteristic (next-state) equation for such latches and flip-flops. State any necessary restrictions on the input signals
3. Given the present state and desired next state of F/F, determine the required F/F/ inputs.
4. Analyze a sequential circuit by signal tracing.
5. Given a problem statement for the design of a Mealy or Moore sequential circuit, find the corresponding state graph and table.
6. Specify a suitable set of state assignments for a state table, eliminating those assignments which are equivalent with respect to the cost of realizing the circuit
7. Design a sequential circuit using gates and flip-flops.
HRD 콘텐츠
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